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rev. 1.2 1/15 copyright ? 2015 by silicon laboratories SI3462-EVB SI3462-EVB si3462 e valuation b oard u ser s g uide 1. introduction this document is intended to be used in conjunction with the si3462 data sheet for designers interested in the following: ?? an introduction to power over ethernet (poe) and po wer sourcing equipment (pse) design considerations ?? operation of the si3462 pse contro ller in the si3462- evb reference design ?? configuration and operation of the SI3462-EVB 2. overview of the si 3462 and evaluation board the si3462 is a single-port power management controlle r for ieee 802.3at poe/poe+ compliant power sourcing equipment (pse). the si 3462 operates dire ctly from a 50 v (nominal) isolat ed input for poe or 54 v (nominal) isolated input for poe+. the complete si3462 refere nce design (i.e., the SI3462-EVB) also provides full ieee-compliant classification and detection as well as a ro bust disconnect algorithm. in telligent protection circuitry includes input under-voltage and over-voltage lockout (u vlo/ovlo), current limiting, and output short-circuit protection. the si3462 is designed to operate completely independen tly of host processor control. a reset button and an optional led status signal are provided to indicate port status including detect, power good, and output fault event information. the si3462 is pin-programmable to support: ?? no classification mode reduces b ill of materials for 15.4 w operation and also for non-standard powered devices that do not present a proper classification signature ?? endpoint and midspan applicat ions with support fo r either 10/100base-t or 10/100/1000base-t ?? all poe/poe+ classification power levels ?? classification-base d current limiting ?? automatic or manual restart after various fault events are detected figure 1. typical application circuit (example is for poe; for poe+, use +54 v nominal v in ) si3462 gnd deta v dd +3.3 v v out 48 v pse output (to port magnetics) rst vdd detect & mark isense gnd status clsmode dc1 clsmark vsense detect fault pgood dc2 v in +50 v gnd + _ +50 v classification & gate drive optional 3.3 v regulator
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB 3. connectors and switches the SI3462-EVB is equipped with two banana jacks and an optional third banana jack on one side and two rj-45 connectors on the other side. figure 2. placement of connectors and switches the board receives power through the banana jacks: ?? j1 black banana jack: gnd ?? j2 red banana jack: +50 v nominal input (+45 v to +57 v) for poe; +54 v nominal input (+51 v to +57 v) for poe+ ?? j3 optional banana jack: +3.3 v input an optional onboard +3.3 v shunt regulator generates the supply voltage for the si3462 from the +50 v input voltage. the +3.3 v supply voltage may also be provided by an external source through the optional banana jack if higher efficiency is desired. in this case, the regulator an d its associated resistors (including the series resistors) should be removed. the rj-45 ethernet connectors: ?? j7 ethernet in input ?? j8 poe output reset pushbutton: ?? sw1 mode setting dip switch: ?? sw2 these switches set the operating mode according to table 2 on page 7 including the following: ?? available power level (4 w, 7 w, 15.4 w, and 30 w) ?? midspan or endpoint configuration ?? automatic restart or restart afte r disconnection modes of operation refer to "6.1. initialization and operating mode configuration" on page 7 for more details.
SI3462-EVB rev. 1.2 3 4. quick check of the si3462 evaluation board the only items needed to operate the si3462 are an is olated 50 v power supply and connection cables (the SI3462-EVB comes with the optional onboard 3.3 v s hunt regulator). for a quick check of the board, perform the following steps: ?? ensure that the configuration dip s witch settings are in line with the powered device (pd) to be used (refer to "6.1. initialization and operating mode configuration" on page 7). alternatively, for the purpose of this quick check, use the settings shown in figure 3. ?? 30 w of available power ?? midspan configuration ?? automatic retry figure 3. dip switch settings ?? connect the 50 v power supply to the banana inputs obse rving the correct polarity (a series diode protects the board from damage in case of polarity reversal). ?? switch on the 50 v power supply. the status led should flash at a 1.5 hz rate signaling that the si3462 is trying to detect a pd. ?? connect a pd to the poe labeled rj-45 connector. af ter a short time, power should be applied to the pd, and the status led should turn continuously on. if th e pd requests more power than the SI3462-EVB is configured for, power will be denied, or, if once po wered and an overload condition occurs, power will be shut down, and the status led will flash rapidly. depending on initial configurat ion, the device may then automatically start detection after 2.2 seconds or wait until the ethernet cable is removed (and plugged in again). 1
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB 5. introduction to poe ieee 802.3 clause 33 is the standard fo r providing power to a re mote ethernet device on the same ca ble that is carrying data. the draft standard for higher power situati ons, often referred to as poe+, is 802.3at. the power is either carried common-mode on one of the data pairs (for 10/100 /1000base-t) or on the spare pairs for 10/100base-t only applications. there are various differen t connection schemes depending on the pairs used to carry the power (alternative a or b), the locati on of power insertion (endpoint or midspan), and 10base-t/100base-tx or 1000base-t compatibility. the SI3462-EVB implem ents the configuration shown in figure 4. midspan pse connectio n (alternative b), but the si3462 controller can be configured to operate in either midspan or endpoint applications and may be designed in applications using any pairs. figure 4. midspan pse connection (alternative b)* *note: this is the connection scheme implem ented on the SI3462-EVB reference design. power sourcing equipment (pse) powered device (pd) tx rx 4 5 1 2 3 6 7 8 s pare pair s ign al p air s ign al p air spare pair 4 5 1 2 3 6 7 8 rx tx dc-dc converter and pd i/f 48 v 4 5 1 2 3 6 7 8 switch/hub 4 5 1 2 3 6 7 8 data pair data pair spare pair spare pair poe ethernet in
SI3462-EVB rev. 1.2 5 5.1. pse detection, classification, power-up, and power removal the basic sequence for applying power is shown in figure 5. the following is a description of the functions that must be performed in each phase. figure 5. detection, classification, power-up, and disconnect sequence 5.1.1. detection during the detection phase, the pse probes with limit ed current and voltage to determine if a 25 k ? signature is present. a valid pd must present between 23.75 and 26.25 k ? in the range of 2.8 to 10 v with an offset (due to the bridge diodes) of up to 1.9 v and a parallel capacitance of between 0.05 and 0.12 f. the SI3462-EVB uses a robust 3-poin t detection sequen ce to avoid inadvertentl y powering and damaging a non-poe-enabled device. for endpoint applications, detection must be comple ted within 500 ms of applying a valid signature. when configured as a midspan, there is a possibility that the pse circuit will co mpete with an endpoint pse, and, as required by the ieee specifications, th e si3462 waits at least two seconds after an unsuccessful detection cycle to repeat the detection process. voltage t det_cycle time (msec) 2.8 v 10 v 15.5 v 44 v 57 v 20.5 v t class_cycle t pwrup
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB 5.1.2. classification classification is performed by applying a voltage betwe en 15.5 v and 20.5 v to the pd and measuring the current. the maximum power level that can be drawn by the pd is determined based on the current measured according to the information in table 1. to save bill of materials cost, the si 3462 does not pe rform classification when co nfigured for 15 .4 w of output power. there is also a programmable mode for no classifi cation and 30 w of output power to support non-standard pds. if no classification is done, the classification components of the bill of materials do not need to be populated. the classification mark components only need to be populated for 30 w mode with classification. 5.1.3. power-up after successful classification (i.e . the pse has enough available power to satisfy the pd's needs), power is applied to v out as long as there is not an overcurrent faul t, disconnect, or input undervoltage (uvlo) or overvoltage (ovlo) condition. the status le d is continuously on wh ile power is applied. the si3462 implements a two-level overload protection sc heme. the output current is limited to ilim, and, additionally, the output is shut down if the current exceeds i cut for longer than 60 ms (for further details, refer to 6.4. power-up or to the si3462data sheet). an overload condition is signaled by a rapidly-flashing status led. if power is removed due to an overload condition, dete ction may automatically restart after a 2.2 s delay, or removing and plugging the ethernet cable might be nece ssary depending on the initial configuration (see 6.1. initialization and operating mode configuration). the st art of a new detection phase is signaled by the led flashing at a lower rate. 5.1.4. disconnect (power removal) removal of a pd can be sensed by determining that the dc current is less than 5 ma for more than 350 ms. if the current then exceeds 10 ma before reaching the timeout for at least 60 ms, the power must not be removed. table 1. classification levels isense current (nominal) classification level minimum power level < 6.5 ma class 0 15.4 w 6.5 ma to 14.5 ma class 1 4 w 14.5 ma to 23 ma class 2 7 w 23 ma to 33 ma class 3 15.4 w 33 ma to 48 ma * class 4 26.4 w *note: currents above 45 ma may be treated as class level 0, which is 15.4 w.
SI3462-EVB rev. 1.2 7 6. detailed description of the si3462 pse controller the si3462 is a fully ieee compliant poe/poe+ pse power management controller. t he si3462 is specifically designed and configur ed to work with an applications circuit (si3 462-evb) with which it implements a single port pse solution for either midspan or endpoint poe applications. refer to the detailed evaluation board schematics in "9. SI3462-EVB schematics" on page 17 and "11. SI3462-EVB pcb layouts" on page 23; th e overall functionality is described be low. representative waveforms are shown in "8. output voltage and load current waveforms" on page 13. 6.1. initialization and op erating mode configuration the si3462 is initialized at powerup or whenever pin 8 (rst) is held low and then allowed to transition high. upon reset (rst asserted low), the voltage at the status pin (as determined by the di p switch and the associated resistor network) is sensed to determine the operating mode of the si3462. the detection process begins immediately after initialization. the following operating mode parameters can be set with the dip switches: ?? endpoint or midspan mode co ntrols the back off timing per ieee specifications. ?? restart action on fault or overload determines whet her the si3462 automatically restarts after 2 s when a fault or overload condition (e.g., input uvlo, outp ut short-circuit event, classification power level exceeded) is detected or waits to restart until an open-circuit condition is sensed. ?? available power level (and pse type specif ying the classification method used). table 2. operating modes 1,2,3,4,5 dip switch configuration status pin voltage (v) operating mode pse type midspan/ endpoint restart action on fault or overload event condition availab le power classification bom 5 , 6 classification mark bom 5 , 7 < 0.122 2 midspan restart after disconnection 30 w no no 0.122 to 0.338 1 midspan restart after disconnection 7w yes no 0.338 to 0.548 1 midspan restart after disconnection 15.4 w no no 0.548 to 0.756 2 midspan restart after disconnection 30 w yes yes notes: 1. after power-up, the status pin drives the base of an npn transistor that controls an led. 2. there is a trade-off in selecting the mode setting resistor values between voltage step accuracy and additional worst-case supply current. for high-value re sistors, the base cu rrent will alter the voltage steps while low-value resistors may place higher load on the status pin while driving the led. the suggested resulting parallel resistance used by the SI3462-EVB is 2.0 k w . 3. each mode setting resistor should be connected either to gnd or +3.3 v through the dip switch. care should be taken not to short the +3.3 v supply to gnd. 4. a reset is required after a dip switch position change for the new mode to take effect. 5. refer to the SI3462-EVB user guide to understand the co mponents required to support classification and mark. 6. classification components are r14,r15,r16c8, d5, q6, and q17. 7. classification mark components are q2, r24, and r25.
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB 0.756 to 0.961 2 midspan auto restart after 2s 30 w no no 0.961 to 1.162 1 midspan auto restart after 2s 7w yes no 1.162 to 1.366 1 midspan auto restart after 2s 15.4 w no no 1.366 to 1.575 2 midspan auto restart after 2s 30 w yes yes 1.575 to 1.784 2 endpoint restart after disconnection 30 w no no 1.784 to 1.990 1 endpoint restart after disconnection 7w yes no 1.990 to 2.196 1 endpoint restart after disconnection 15.4 w no no 2.196 to 2.407 2 endpoint restart after disconnection 30 w yes yes 2.407 to 2.618 2 endpoint auto restart after 2s 30 w no no 2.618 to 2.838 1 endpoint auto restart after 2s 7w yes no 2.838 to 3.044 1 endpoint auto restart after 2s 15.4 w no no >3.044 2 endpoint auto restart after 2s 30 w yes yes table 2. operating modes 1,2,3,4,5 (continued) dip switch configuration status pin voltage (v) operating mode pse type midspan/ endpoint restart action on fault or overload event condition availab le power classification bom 5 , 6 classification mark bom 5 , 7 notes: 1. after power-up, the status pin drives the base of an npn transistor that controls an led. 2. there is a trade-off in selecting the mode setting resistor values between voltage step accuracy and additional worst-case supply current. for high-value re sistors, the base cu rrent will alter the voltage steps while low-value resistors may place higher load on the status pin while driving the led. the suggested resulting parallel resistance used by the SI3462-EVB is 2.0 k ? . 3. each mode setting resistor should be connected either to gnd or +3.3 v through the dip switch. care should be taken not to short the +3.3 v supply to gnd. 4. a reset is required after a dip switch position change for the new mode to take effect. 5. refer to the SI3462-EVB user guide to understand the co mponents required to support classification and mark. 6. classification components are r14,r15,r16c8, d5, q6, and q17. 7. classification mark components are q2, r24, and r25.
SI3462-EVB rev. 1.2 9 after power-up, the status pin of the si3462 is in a hi gh-impedance state and is used for measuring the voltage set by the dip switch and the associated resistor network. then, during normal operation, this pin drives the status led via transistor q3. the mode setting voltage steps are provided by a simple 4-bit dac. each mode setting resistor should be connected either to gnd or +3.3 v for proper operation. take care not to short the +3.3 v supply to gnd, and remember to activate the reset button for the new configuration to take effect. the voltage thresholds found in table 2 on page 7 take into account the slight loading effect of q3's base current; therefore, it is recommended to use the same source resistance (around 2.0 k ? ) as that of the SI3462-EVB network when providing the status pin voltage from a differ ent voltage source, such as a simple voltage divider or a dac. different resistor values may be used in the mo de setting network, but the trade-off between voltage step accuracy and the additional worst-case supply current sh ould be considered. for high value resistors, the base current will alter the voltage steps, wh ile low value resistors may place hi gher loads on the status pin when driving the led. 6.2. detection the detection process consists of sensing a nominal 25 k ? signature resistance in parallel with up to 0.15 f of capacitance. the signature resistance measurement has to be carried out in the 2.8 to 10 v output voltage range with a 5 ma current limit. to eliminate the possibility of false detection events, the si346 2-evb reference des ign performs a robust 3-point detection sequence by varying the voltage across the load and sensing the load current changes. this minimizes effects, such as those caused by the diode bridges present in powered devices (pds). at the beginning of the detection sequence, v out is at zero; then, it is varied from 4 to 8 v and back to 4 v for 20+20+50 ms at each respective level. if the pd's signature resistance is in the rgood range of 17 to 29 k ? , the si3462 proceeds to classification and powerup. if the pd resistance is not in this range, the detection sequence repeats continuously. detection is sequenced approximately every 360 ms unt il rgood is sensed, indicating a valid pd has been detected. the status led (d2) is flas hed at an approximate rate of 1.5 hz to indicate that the pse is searching for a valid pd. 6.3. classification to save bill of materials cost, the si 3462 does not pe rform classification when co nfigured for 15 .4 w of output power. there is also a pin-programmable mode for no classification and 30 w of output power to support non-standard pds. if no classifi cation is done, the classifi cation components of the b ill of materials do not need to be populated. the classification mark components only need to be populated for 30 w mode with classification. the si3462 implements both the one-event and two-even t physical layer classifica tion methods. for one-event classification, the pass fet q4 is turned on and progra mmed for an output voltage of 18 v with a current limit of 75 ma for 30 ms. for the two-event classification, the 18 v pulse is output twice with an 8.5 v amplitude mark pulse for 10 ms between the two classification pulses. if the class level of the pd is not within the supported level as set by the initial voltage on the si3462's status pin (refer to the operating mode configuration section above), an error is declared, and the led blinks rapidly at a rate of 10 hz for two seconds before the si3462 goes back to the detection cycle. this is referred to as classification-based power denial. if the class level is in the supported range, the si3462 proceeds to powerup. this is referred to as classification-based power gran ting. classification level is determined according to the current measured at the isense input as shown in table 3.
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB 6.4. power-up after successful classification, the pass fet is turned on with a current limit corresponding to the classification results as indicated in table 3. after powerup, power is applied to v out as long as there is no overcurrent fault, disconnect, or input under-voltage (u vlo) or over-voltage condition. the status led is continuously lit when power is applied. if the output power exceeds t he level of the power requested during classification, the si3462 will declare an error and shut down the port, flashing the led rapidly to indicate the error (for either two se conds or until an open-circuit condition is detected as determined by the initial voltage on the status pin). the SI3462-EVB implements two leve ls of overload protection: ?? the output current is limited to the ilim value corres ponding to the classification level detected (refer to table 3). during the powerup transient, phase output current is limited to 425 ma, independent of the classification level. ?? if the output current exceeds i cut for longer than 60 ms, the output is shut down (refer to table 3 for the i cut values). additionally, for class 4 devices, if cu rrent limitation persists longer than 15 ms, power will also be shut down to protect the pass fet. if the si3462 was configured to operat e in the automatic retry mode, it will retry detect ion and power up after an overload. in this case, the status led will flash rapidly fo r two seconds to show the error condition, and then the si3462 will automatically initiate a new detection cycle while the status led flashes at a rate of 1.5 hz. alternatively, the si3462 can be progra mmed to signal that an error conditi on has occurred, in which case the user must disconnect the ethernet cable and plug it in again (or push the reset switch on the SI3462-EVB) to start a new detection and powerup cycle. in this case, the status led flashes rapidly until an open-circuit is detected and then flashes at a rate of 1.5 hz to show th at a new detection cycle is in progress . power is provided again only after successful detection and classification . the SI3462-EVB does not regulate th e output voltage during the power-on state. input voltage c hanges will be transmitted to the output directly. 6.5. disconnect (power removal) the si3462 supports a robust disconnect algorithm. if the output current drops below 7.5 ma, a timer is started to count towards a time-out of 350 ms. if the output current again exceeds the 7.5 ma threshold, the timer is decremented at 10 times the increment rate towards zero. power is removed from the output if the timer reaches the 350 ms limit, but the si3462 will contin ue to provide power if the output current is ab ove the 7.5 ma limit for at least a fraction of the 350 ms timeout (unless an overload condition is sensed). the only other way to force the si3462 to disconnect power is by doing a reset. table 3. classification levels isense current (nominal) classification level pse type minimum power level overload current threshold i cut (typ) [ma]* overload current limit i lim (typ) [ma] < 6.5 ma class 0 1 15.4 w 16,500/vout 425 14.5 ma to 23 ma class 2 1 7 w 7,500/vout 425 23 ma to 33 ma class 3 1 15.4 w 16,500/vout 425 33 ma to 48 ma class 4 2 26.4 w 33,200/vout 885 *note: the i cut overload thresholds are dyna mically calculated as a function of the granted power and the effective output voltage.
SI3462-EVB rev. 1.2 11 6.6. current limit control the si3462's overcurrent trip point, i cut , is determined by the output power set during the classification stage power granting process and the actual output voltage. if the output current exceeds the threshold, a timer counts up towards a timeout of 60 ms. if the current drops below the set threshold, the timer counts down towards zero at 1/16th the rate. if the timer reaches the set timeout, an overcurrent fault is declared, and the channel is shut down by turning off the pass fet. additionally, for class 4 devices, if the output current reaches the ilim level, the output is shut down after 15 ms to protect th e pass fet. after an overcurrent fault event, the led will flash rapidly. as set by the initial voltage on the status pin at powerup, the si3462 then automa tically resumes the detection process for automatic restart configuration unless the si3462 is co nfigured in a restart after a disconnect condition mode. for the automatic restart configuration, the led will flas h rapidly after an overcurrent event for 2.2 seconds, and a new detection cycle will be init iated. the led will then flas h at a 1.5 hz rate to show that the detection is in progress. in the restart on disconnect configur ation, the led will flash rapidly until an open-circuit condition is detected before a new dete ction cycle will start. normally, an open-circuit conditio n can be created by removing the ethernet cable from the SI3462-EVB's rj-45 jack labelled poe. power will not be provided until an open- circuit condition is detected. once the si3462- evb detects an open-circuit co ndition, the detection proc ess begins. the status led blinks at a rate of 1.5 hz, and the si3462 is then allowe d to go into classification and powerup mode if a valid pd signature resistance is detected. 6.7. uvlo/ovlo the SI3462-EVB referenc e design is optimized for 50 v nominal input voltages (44 v minimum to 57 v maximum). if the input voltage drops below 42 v, a uvlo condition is declared, or, if it exceeds 60 v, an over-voltage condition is declared, and the output is shut dow n in both cases. an undervoltage or an overvoltage event is a fault condition reported through the status led as a rapid blinking of 10 flashes per second. the uv lo and ovlo conditions are continuously monitored in all operating states. 6.8. status led function during the normal detection sequence, the status led flashes approximately 1.5 times per second as the detection process continues. after succe ssful powerup, the led glows continuously. if there is an error condition (i.e., class level is beyond the programmed value or a fault or overcurrent condition has been detected), the led flashes rapidly at 10 times per second. this occurs fo r two seconds for normal error delay, and the detection process automatically starts again after 2.2 s unless a resta rt after disconnect condition was set during the initial configuration. power will not be provi ded until an open-circuit condition is detected. once t he SI3462-EVB detects an open-circuit condition, the led blinks at 1.5 times per second. if the pd is disconnected so that a disconnect event occurs, the led starts fl ashing at 1.5 times per second once the detect process resumes.
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB 7. design and layout considerations 7.1. general recommendations the SI3462-EVB schematic and layout are intended to be used as a reference for all customer designs. the SI3462-EVB has been tested by the university of new ha mpshire intero perability lab (unh iol) to comply with the relevant ieee 802.3 clause 33 specifications . unh test reports can be downloaded from http://www.silabs.com/poe . since the si3462's performance in an application depends on external components and pcb layout, customers are ultimately responsible fo r validating their design's conformance to all relevant industry, safety, and customer-specific requirements. for applicat ions support, visit the silicon labs technical support web page: https://www.silabs.com/support/page s/contacttechnicalsupport.aspx . 7.2. isolation the ieee 802.3 specification requires that the pse output power be isolated from earth ground*. to accomplish this, the input power source must be isolated from earth ground. also, do not connect the si3462's ground connection (pin #11) to earth ground because this pin serves only as a ci rcuit reference poin t in the SI3462-EVB. *note: if the input power supply is referenced to earth ground and if one of the output pads is connected to ground, it can create a high-current fault condition that will not be protected. 7.3. selv-compliant output voltage since the output of the si34 62-evb reference design is designed to be less than 57 vdc under all co nditions, it is considered an selv circuit. 7.4. surge protection the SI3462-EVB applications design includes a clamp diode , d6, to protect against 50 s intra-building lightning surges as specified in ieee 802.3. addi tional protection, such as a 1 a fuse in the output circuit, may be required for applications in which the ether net cabling is not intra-building. 7.5. thermal considerations the pass fet needs a cooling surface of adequate size. the si3462 controller itself implements over-temperature protection, but this alone cannot effe ctively protect the pass fet in case of a sudden overload. nevertheless, relatively tight thermal coupling between the two devices may be a good idea. some of the resistors, such as the current sensor and the series resistors of the shunt regulator (if used), also dissipate relatively large amounts of power. care shoul d be taken to select resistors with proper power ratings. using a high-efficiency external 3.3 v supply instead of the onboard shunt regu lator can save almost 1 w of power.
SI3462-EVB rev. 1.2 13 8. output voltage and load current waveforms figures 6 through 13 show the output voltage and load current waveforms during startup and fault conditions. refer also to the SI3462-EVB schematics in figures 14 through 16. figure 6. detection pulse into open-circuit figure 7. successful detection ch 1 : poe output vo ltage referenced to the +50 v rail with the output open slow decay due to the 453 k pull -up ba d detection signature de tected at this point ch1: poe output voltage referenced to the +50v rail good detection signature detected at this point
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB figure 8. detection and classification pulse for a type-1 device figure 9. detection and classification pulse for a type-2 device ch1: poe output voltage referenced to the +50v rail detection classification ch1: poe output voltage referenced to the +50v rail detection two event classification mark pulse
SI3462-EVB rev. 1.2 15 figure 10. detection, classification, and powerup for a type-1 device figure 11. detection, classification, and power-up for a type-2 device ch1: poe output voltage referenced to the +50v rail detection classification power-on ch1: poe output voltage referenced to the +50v rail detection power-on two event classification mark pulse
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB figure 12. overcurrent disconnect delay time of 60 ms figure 13. overcurrent disconnect delay time of 15 ms
SI3462-EVB rev. 1.2 17 9. SI3462-EVB schematics full schematics are provided in the following figures. to ensure you are using the latest schematic database revisions, you may download the zi p file from the silicon laboratories si3462 documentation page: http://www.silabs.com/products/power/poe/pages/powersourcingequipment.aspx ethernet ports input power connector 3.3v regulator reset button controller poe load detector common mode chokes for gbe midspan uvlo 10v driver dc1 is lsb for current limit and msb for detection dc1 is lsb for current limit and msb for detection gate drive classification and current limiting to the poe load detector not populated optional classification components optional classification mark components status /rst vsense poe- +50v +50v poe- classmark dc1 dc2 classmode deta vsense isense status /rst 0 +3v3 +3v3 0 0 0 +3v3 +50v 0 0 +50v 0 +50v +50v 0 +50v 0 +50v 0 +50v +3v3 +3v3 +3v3 +3v3 0 classmode deta classmark dc2 dc2 isense dc1 dc1 poe- dc1 classmark classmode isense deta poe- q3 mmbta06lt1 r25 10k r17 453k tpv8 r8 549k mode_sw mode_sw 3.3v gnd md c10 0.1uf c14 0.1uf q6 mmbta06lt1 r7 332 tpv6 q2 mmbta06lt1 c12 0.01uf c9 470pf d4 mmsd914 c8 0.01uf tpv14 tpv11 r6 1.5k r24 10k r20 301k u2 tlv431 r11 20k r13 9.09k tpv4 r19 1k j8 rj-45 mx0+ 1 mx0- 2 mx1+ 3 mx2+ 4 mx2- 5 mx1- 6 mx3+ 7 mx3- 8 r14 2.37k c15 0.1uf c5 1uf u1 si3462 pse clsmark 1 dc1 2 dc2 4 clsmode 5 deta 6 vsense 7 isense 9 status 10 rst 8 vdd 3 gnd 11 j7 rj-45 mx0+ 1 mx0- 2 mx1+ 3 mx2+ 4 mx2- 5 mx1- 6 mx3+ 7 mx3- 8 c4 1uf j2 red c13 0.1uf d6 smaj58a q17 bc856a r27 4.99k tpv1 q5 mmbta06lt1 r1b 5.11k r4 40.2k j1 black tpv3 c1 0.1uf r18 2.00 r2 1k q14 bc856a r3 66.5k d7 mmsd914 socket socket vdd gnd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 /rst r1a 5.11k q1 mmbta06lt1 r9 2.15k q4 irfm120a d1 s1b r12 20k r28 10k c6 0.01uf r5 49.9k tpv13 tpv9 tpv10 q16 bc856a r26 20k r10 10k c16 0.1uf d2 green c7 15nf + c3 12uf r15 20k l1a fa2536-ald 1 2 3 r16 36.5k tpv2 tpv7 r23 20.0k j3 red d5 16v r22 5.11k tpv5 tpv12 d3 mmsd914 r29 10k c11 470pf s1 sw pushbutton c2 10uf c17 0.1uf r21 10k l1b fa2536-ald 6 5 4 figure 14. SI3462-EVB schematic (1 of 3)
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB operating mode 3.3v gnd md 0 r100 3.24k r100 3.24k r101 6.49k r101 6.49k r102 13.0k r102 13.0k sw2 sw dip-8 sw2 sw dip-8 r103 26.1k r103 26.1k figure 15. SI3462-EVB schematic (2 of 3)
SI3462-EVB rev. 1.2 19 /rst c2ck p0.7 c2dat vdd gnd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 /rst 0 0 0 j11 df9-9s-1v j11 df9-9s-1v 1 2 3 4 5 6 7 8 9 j10 df9-9s-1v j10 df9-9s-1v 1 2 3 4 5 6 7 8 9 figure 16. SI3462-EVB schematic (3 of 3)
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB 10. SI3462-EVB bill of materials table 4. SI3462-EVB bill of materials qty ref value rating tol pcb footprint mfr part number mfr poe bom (including optional led) 2 c1, c10 0.1 f 10 v c0603 c0603x7r101-104k venkel 1 c2 10 f 6.3 v c0603 c0603x5r6r3-106m venkel 1 c5 1 f 10 v c0603 c0603x7r100-105k venkel 2 c6, c12 0.01 f 100 v c0603 c0603x7r101-103k venkel 1 c7 15 nf 16 v c0603 c0603x7r160-153k venkel 2 c9, c11 470 pf 25 v c0603 c0603x7r101-471k venkel 1 c17 0.1 f 10 v c0603 c0603x7r100-104k venkel 1 d2 green 25 ma led-rt 551-0207 dialight 3 d3, d4, d7 mmsd914 0.2 a sod-123 mmsd914 fairchild 1 d6 smaj58a 400 w do-214ac smaj58a littelfuse 4q1, q2, q3, q5 mmbta06lt1 500 ma sot23-bec mmbta06lt1 on semi 1 q4 irfm120a 2.3 a sot223-gds irfm120a or fdt3612 fairchild 2 q14, q16 bc856a 100 ma sot23-bec bc856a diodes inc. 1r19 1k ? 1/16 w 1% r0603 cr0603-10w-1001f venkel 1r5 49.9k ? 1/8 w 1% r0805 cr0805-8w-4992f venkel 1r6 1.5k ? 1/10 w 1% r0603 cr0603-10w-1501f venkel 1r7 332 ? 1/16 w 1% r0603 cr0603-10w-3320f venkel 1r8 549k ? 1/16 w 1% r0603 cr0603-10w-5493f venkel 1r9 2.15k ? 1/16 w 1% r0603 cr0603-10w-2151f venkel 3r10, r21 10k ? 1/16 w 1% r0603 cr0603-10w-1002f venkel 4 r11, r12, r15, r26 20 k ? 1/16 w 1% r0603 cr0603-10w-2002f venkel 1 r13 9.09 k ? 1/16 w 1% r0603 cr0603-16w-9091f venkel 1 r17 453 k ? 1/10 w 1% r0805 cr0805-10w-4533f venkel 1r18 2 ? 2 w 1% r2512 cr2512-2w-2r00f venkel 1 r20 301 k ? 1/16 w 1% r0603 cr0603-10w-3013f venkel 1 r22 5.11 k ? 1/16 w 1% r0603 cr0603-10w-5111f venkel
SI3462-EVB rev. 1.2 21 1 r23 20 k ? 1/16 w 1% r0603 cr0603-16w-2002f venkel 1 r27 4.99 k ? 1/16 w 1% r0603 cr0603-16w-4991f venkel 3 r28, r29, r100 10 k ? 1/16 w 1% r0603 cr0603-16w-1002f venkel 1r100 3.24k ? 1/16 w 1% r0603 cr0603-16w-3241f venkel 1 u1 si3462 pse qfn10n3x3p0.5 si3462xyy-gm silabs basic bom optional classification bom 1 r14 2.37 k ? 1/16 w 1% r0603 cr0603-10w-2371f venkel 1 r15 20 k ? 1/16 w 1% r0603 cr0603-10w-2002f venkel 1r16 36.5k ? 1/10 w 1% r0805 cr0805-10w-3652f venkel 1 q6 mmbta06lt1 500 ma sot23-bec mmbta06lt1 on semi 1 q17 bc856a 100 ma sot23-bec bc856a diodes inc. 1 d5 16 v 500 mw 5% sod-123 mmsz5246bt1g on semi 1 c8 0.01 f 100 v c0603 c0603x7r101-103k venkel optional classification mark bom 2r24, r25 10k ? 1/16 w 1% r0603 cr0603-10w-1002f venkel 1 q2 mmbta06lt1 500 ma sot23-bec mmbta06lt1 on semi system dependent bom mode selector 1 sw2 sw dip-8 0.025 a sw8-dip-smt tda08h0sk1 cts 1r101 6.49k ? 1/16 w 1% r0603 cr0603-16w-6491f venkel 1r102 13k ? 1/10 w 1% r0603 cr0603-10w-1302f venkel 1r103 26.1k ? 1/16 w 1% r0603 cr0603-16w-2612f venkel reset 1r2 1k ? 1/10 w 1% r0603 cr0603-10w-1001f venkel 1s1 sw pushbutton 50 ma sw-pb-mom 101-0161-ev mountain switch table 4. SI3462-EVB bill of materials (continued) qty ref value rating tol pcb footprint mfr part number mfr
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB poe coupling circuit for midspan 4 c13, c14, c15, c16 0.1 f 10% c1210 c1210x7r251-104k venkel 1 l1 fa2536-ald 675 h ind-fa2536 fa2536-ald coilcraft connectors 1 j1 black 15 a binding-post 111-0703-001 johnson/emerson 2 j2, j3 red 15 a binding-post 111-0702-001 johnson/emerson 2 j7, j8 rj-45 rj-45 95001-2881 molex 2 j10, j11 df9-9s-1v 0.1 a conn-df9-9s-1v df9-9s-1v hirose electric co. ltd. power input filter 1 d1 s1b 1.0 a do-214ac s1b fairchild 1 c3 12 f 20% c2.5x6.3mm-rad eeufc2a120 panasonic 1 c4 1 f 10% c1210 c1210x7r101-105k venkel 3.3 v supply 2r1b, r1a 5.11k ? 2 w 1% r2512 cr2512-2w-5111f venkel 1 u2 tlv431 tlv431-dbz tlv431bcdbzr ti 1r3 66.5k ? 1/10 w 1% r0603 cr0603-10w-6652f venkel 1r4 40.2k ? 1/10 w 1% r0603 cr0603-10w-4022f venkel table 4. SI3462-EVB bill of materials (continued) qty ref value rating tol pcb footprint mfr part number mfr
SI3462-EVB rev. 1.2 23 11. SI3462-EVB pcb layouts full pcb layouts are provided in the following figures. to ensure you are using the late st layout database revisions, you may download the zip file from the silicon laboratorie s si3462 documentation page: http://www.silabs.com/products/power/poe/pages/powersourcingequipment.aspx figure 17. SI3462-EVB top-side component placement
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB figure 18. SI3462-EVB top-side interconnect
SI3462-EVB rev. 1.2 25 figure 19. SI3462-EVB ground plane
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB figure 20. SI3462-EVB power plane
SI3462-EVB rev. 1.2 27 figure 21. SI3462-EVB bottom-side interconnect
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB 12. bom component considerations to achieve optimal performance and full- specification compliance, silicon labs strongly en courages the use of the components and vendor part numbers listed in 10. SI3462-EVB bill of material s. if alternate components must be substituted, note the following recommendations for components in the power section. ?? diode d6 must not clamp at 57 v and must clamp to <100 v under worst-case surge conditions. ?? heat dissipating components must be separated from each other and moved away from components that are heat-sensitive. other component considerations: ?? headers j10 and j11 are used for development purposes only. the si3462 is not user-programmable, and it is not recommended that these components be included in actual layouts. ?? the operating mode setting dip switch and its associ ated resistors are probably not needed in a custom design. replace them with a suitable voltage divider consisting of two resistors (preferably with a resulting 2.0 k w parallel resistance). ?? diode d1 protects the circuit from accidental polarity reversal. it may not be needed. ?? the reset push button and its associated components (r2 and c5) are optional. if not needed, tie the /rst input high. ?? a much higher-efficiency external supply may be substituted for the 3.3 v shunt regulator.
SI3462-EVB rev. 1.2 29 13. operating the SI3462-EVB the SI3462-EVB itself is very simple to us e. only a 50 v dc power source is needed for connection to j2. a power rating of at least 35 w is recommended when the high-power poe+ mode is used. the si3462 will automatically power up, detect the operational modes (mi dspan/endpoint, classification power level, and restart mode), and begin the detection proce ss, during which the led flashes at 1.5 times per second. figure 22. SI3462-EVB to test the SI3462-EVB in a poe environment, many co mmercial pds are available, such as wireless access points (waps), voice over ip phones (voip), and ip-based security cameras. any of t hese can be connected to the SI3462-EVB to receive pse power while exchanging ethernet traffic. one ex ample of a poe+ pd is an 802.11n (multi-radio) wireless access point. to test the SI3462-EVB in a poe environment, many co mmercial pds are available, such as wireless access points (waps), voice over ip phones (voip), and ip-based security cameras. any of t hese can be connected to the SI3462-EVB to receive pse power while exchanging et hernet traffic. another pd option is to us e the SI3462-EVB with one of the si34 00/01 or si3402 evaluatio n boards co nfigured to present a class 4 load if poe+ is desired. if one of these boards is used, it should be configured to present a minimum load of > 0.25 w to ensure that it draw s at least 10 ma to comp ly with the ieee standard. when the si3462 is applying power to a valid pd, the le d is continuously lit. after an error condition (e.g., an uvlo or short-circuit ev ent) is detected, the led flashes at 10 times per second . the flashing will continue for 2.2 seconds or until an open circuit is detected as determined by the operatin g mode of the si3462. the si3462 mode is set by the voltage levels provided by resistors r100 through r103 and dip switch sw2 according to table 2 on page 7. note that each resistor should be connected to either the 3.3 v supply rail or to ground in order to generate correct voltages (i.e. the two corresponding switches should be in opposite positions). odd-numbered switches connect the resistors to the 3. 3 v supply, and even-numbered switches connect them to ground. the msb is controlled by switches 1 and 2. after changing the settings, push the reset button for the new mode to take effect. the reference board is shipped configured for midspan power injection with full power support and automatic retry after a fault (dip switch setting 01101010).
SI3462-EVB rev. 1.2 4/12 copyright ? 2012 by silicon laboratories SI3462-EVB 14. summary with its fully-compliant pse in terface, the SI3462-EVB provides a si mple and comprehensive applications solution for pse system designers w ho require ieee-compliant pse functiona lity and safe oper ation with standard telephone interfaces and voltages. 15. ordering guide ordering part nu mber description SI3462-EVB evaluation board kit for SI3462-EVB reference design. si3462-xyy-gm ordering part number for si3462 devices. x = device revision; yy = firmware revision. refer to the si3462 data sheet ordering guide for current ordering information.
SI3462-EVB rev. 1.2 31 d ocument c hange l ist revision 1.0 to revision 1.1 ?? updated "15. ordering guide" on page 30. ?? updated ordering part number to SI3462-EVB. revision 1.1 to revision 1.2 ?? updated figure 14 on page 17.
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